With advances in technology and the miniaturization of device elements in semiconductor integrated circuits, integrated circuits are becoming more susceptible to damage due to electrostatic discharge (ESD). In some applications, device elements have reached the submicron level in size and, correspondingly, MOS gate oxide films have become increasingly thin. As a result, the internal circuitry of an integrated circuit device is easily damaged by an ESD event.
Electrostatic discharge may be introduced into an integrated circuit in a variety of ways. One problematic ESD event occurs when ESD zapping occurs on DC power pads of an integrated circuit. A spike, such as an ESD spike, is not a DC voltage, but rather has a power spectrum containing only finite frequency components. Typically, this power spectrum lies in an interval around a characteristic frequency. Usually, the ESD spike will have a rise time of less than about one nanosecond.
Some conventional approaches to addressing this problem are illustrated in FIGS. 1A, 1B, 1C, and 1D, which illustrate conventional ESD protection circuits 100, 120, 140, and 160, respectively.
With reference to FIG. 1A, a high voltage Vcc is applied to high voltage pad 102 and a ground voltage is applied to ground pad 104. The ground voltage may be referred to as Vss. The circuit 100 includes a trigger circuit 106 and a discharge circuit 108. The trigger circuit 106 is coupled between the high voltage pad 102 and the ground pad 104 and provides a trigger signal at node 114.
The discharge circuit 108 is also coupled between the high voltage pad 102 and the ground pad 104. In response to the trigger signal, the discharge circuit 108 is capable of shunting charge, such as an electrostatic discharge, from the high voltage pad 102 to the ground pad 104. The discharge circuit 108 may include NMOS transistor 110, the gate of which is connected to node 114 and is controlled by the trigger signal Vtr.
In an ESD event, the trigger circuit 106 alters the trigger signal Vtr and turns on the discharge circuit 108. The trigger circuit 106 includes a capacitor 112 connected between the high voltage pad 102 and the node 114 and a resistor 116 connected between the ground pad 104 and the node 114, with the capacitor 112 and the resistor 116 being arranged in series. The resistor 116 may comprise an NMOS transistor or other resistive element. The R*C range of the resistor 116 and the capacitor 112 of the circuit 100 of FIG. 1A is typically in the range of a few hundred nanoseconds to a few micro-seconds.
During an ESD event (i.e., an ESD zap at the high voltage pad 102) the voltage at node 114 goes high, thus turning on the discharge circuit 108 by placing a high voltage at the gate of the NMOS transistor 110, thereby turning on the transistor 110 and permitting current flow from the high voltage pad 102 through the transistor 110 to the ground pad 104. Hence, during an ESD event, the circuit 100 is capable of shunting an electrostatic discharge zap at the power pad 102 to the ground pad 104.
During normal operation, however, if on the high voltage pad 102, Vcc has high positive spikes, the trigger circuit 106 will turn on the discharge circuit 108, thus causing current to flow from high voltage pad 102 through the transistor 110 to ground pad 104. This results in unnecessary power consumption and unnecessary noise during normal operation.
In particular, in the circuit 100 of FIG. 1A, when Vcc has a high positive spike greater than the threshold voltage of the transistor 110, the transistor 110 will turn on (i.e., become highly conductive) and will permit current flow from the high voltage pad 102 to the ground pad 104.
The circuits 120, 140, and 160 of FIGS. 1B, 1C, and 1D comprise variations of the circuit 100. The circuit 120 of FIG. 1B is identical to the circuit 100 of FIG. 1A, except that the positions of the resistor 116 and the capacitor 112 are reversed and the NMOS transistor 110 is replaced with a PMOS transistor 111. The circuit 140 of FIG. 1C identical to the circuit of FIG. 1A, except that the positions of the resistor 116 and the capacitor 112 are reversed and an inverter 142 is positioned between the node 114 and the gate of the NMOS transistor 110. The circuit 160 of FIG. 1D is identical to the circuit 100 of FIG. 1A, except that the NMOS transistor 110 is replaced with a PMOS transistor 161 and an inverter 162 is positioned between the node 114 and a gate of the PMOS transistor 161.
Thus, in the circuits 100 and 120 of FIGS. 1A and 1B, when a positive Vcc spike occurs that is greater than the threshold voltage of the respective transistor 110, 111, the discharge circuit 108 will start to flow current. In the circuits 140 and 160 of FIGS. 1C and 1D, when the positive Vcc spike is greater than the threshold voltage, the inverters 142, 162 will start to flow current.
U.S. Pat. No. 6,069,792 and R. Merrill and E. Issaq, “ESD Design Methodology,” 1993 EOS/ESD Symposium Proceedings, pp. 223–237, and K. Seshan, T. Maloney, K. Wu “The Quality and Reliability of Intel's Quarter Micron Process,” Intel Technology Journal, Q3 '98, disclose additional background information and are all hereby incorporated by reference.